1. Field of the Invention
The invention relates to clock extraction circuits used in digital communication, and in particular, to a clock recovery circuit implemented by early-late gate.
2. Description of the Related Art
In digital communication, receiving ends use clock recovery circuits to extract clocks from received data for establishing bit synchronization therewith. Thus, receiving ends can judge and read the received data correctly.
In wireless communication, such as Bluetooth, the clock recovery circuit is implemented by an early-late gate circuit. FIG. 1 is a block diagram illustrating an early-late gate recovery circuit in prior art. As shown in FIG. 1, the early-late gate recovery circuit comprises an early sample circuit 102, an early accumulator circuit 104, a mid-sample circuit 106, a late sample circuit 108, a late accumulator circuit 110, an adder 111, a loop filter 112 and a controlled counter 114. Received data In is input to the early-late gate recovery circuit. In the early-late gate recovery circuit, the received data is detected by the early sample circuit 102, mid-sample circuit 106 and late sample circuit 108. An output signal of the mid-sample circuit 106 is input to the adder 111. The adder 111 performs operations of an output signal of the early accumulator circuit 104 and an output signal of the late accumulator circuit 110 according to the output signal of the mid-sample circuit 106. The operational result is input to the loop filter 112. The loop filter 112 judges whether to adjust an impulse-producing time to make the controlled counter 114 produce an output clock in an ideal range.
The conventional early-late gate recovery circuit slightly adjusts the output clock according to the received data. It takes a long time for the conventional early-late gate recovery circuit to adjust the output clock to stable status (the balance of the early gate and the late gate). FIG. 2 is a schematic illustrating the output clock adjusted by the conventional early-late gate recovery circuit. Line 20 is a graph showing the received data In received by the conventional early-late gate recovery circuit. The dotted line of the line 20 is the noise of received data. Line 22 is the graph showing the output clock of the conventional early-late gate recovery circuit. As shown in FIG. 2, the conventional early-late gate recovery circuit slightly adjusts the output clock according to the received data In. It takes a long time for the conventional early-late gate recovery circuit to adjust the output clock to stable status (the balance of the early gate and the late gate). At the adjusted time, symbol jitter is too large to allow the received end to judge and read the received data correctly or the received end cannot receive packets transmitted from the transmitted end correctly. The large symbol jitter loses the transmitted packets and reduces transmission quality.